Why Stacking Chips Like Pancakes Could Mean a Huge Leap for Laptops

For decades, you could test a computer chip’s mettle by how small and tightly packed its electronic circuitry was. Now Intel believes another dimension is as big a deal: how artfully a group of such chips can be packaged into a single, more powerful processor.

At the Hot Chips conference Monday, Intel Chief Executive Pat Gelsinger will shine a spotlight on the company’s packaging prowess. It’s a crucial element to two new processors: Meteor Lake, a next-generation Core processor family member that’ll power PCs in 2023, and Ponte Vecchio, the brains of what’s expected to be the the world’s fastest supercomputer, Aurora.

Advanced packaging, which lets chip designers link several “chiplets” into one larger processor, is key to making future PCs faster and more capable. The technology is how AMD builds its top-end PC processor, the Ryzen 7 5800X3D, and how Apple glues two M1 Max chips into the M1 Ultra, its most powerful Mac processor.

But that Ryzen chip retails for $440, and the M1 Ultra adds $2,000 to the price of an M1 Max Mac Studio. Meteor Lake brings packaging to the mainstream PC market, where consumers buy hundreds of millions of machines annually, even in bad years. The advancement will lead to faster, more powerful computers without an eye-popping price tag.

“Meteor Lake will be a huge technical innovation,” thanks to how it packages, said Real World Tech analyst David Kanter.

For decades, staying on the cutting edge of chip progress meant miniaturizing chip circuitry. Chipmakers make that circuitry with a process called photolithography, using patterns of light to etch tiny on-off switches called transistors onto silicon wafers. The smaller the transistors, the more designers can add for new features like accelerators for graphics or artificial intelligence tasks.

Now Intel believes building these chiplets into a package will bring the same processing power boost as the traditional photolithography technique.

“We’re at that point where packaging is as important as the process technology itself,” said Boyd Phelps, leader of Intel’s Design Engineering Group, in an interview.

Packaging technology matters to Intel. It’s struggling to reclaim chipmaking leadership lost to Taiwan Semiconductor Manufacturing Co. (TSMC), which makes Apple chips, and to Samsung. Even as it spends tens of billions of dollars on new chipmaking capacity, though, its most recent quarterly financial results were “disastrous,” TechInsights analyst Linley Gwennap said. A $52.7 billion chipmaking subsidy from the US government won’t help until 2023.

Packaging could help Intel get back some of its onetime lead.

Intel co-founder’s 1965 prophecy comes true

Intel co-founder Gordon Moore predicted a “day of reckoning” in which it no longer makes sense to make chips out of a single large slice of silicon. In his seminal paper laying out Moore’s Law, he wrote, “It may prove to be more economical to build large systems out of smaller functions, which are separately packaged and interconnected.”

Intel has two main packaging approaches.

First is EMIB (Embedded Multi-die Interconnect Bridge), which links two “chiplets” side by side with a small connecting patch underneath. That’s used in Ponte Vecchio and higher end models of its upcoming Sapphire Rapids server processor.

Second is Intel’s Foveros, which joins multiple chiplets vertically, like plopping one pancake on top of another. The Meteor Lake chip is built with Foveros, with four chiplets perched on another silicon substrate below that provides communication links.

Foveros is also key to Meteor Lake’s successor, Arrow Lake, which will benefit from upgraded circuitry for its central processing unit (CPU) and graphics processing unit (GPU) cores. After that comes Lunar Lake, designed for laptops with very low power consumption, and featuring an updated recipe of chiplet ingredients. Both Arrow Lake and Lunar Lake should be “ready in 2024,” Phelps said.

EMIB and Foveros both help extend Moore’s Law’s trend of increasing transistor counts. The Ponte Vecchio supercomputer chip, for example, has more than 100 billion transistors.

Advanced packaging advantages

One big advantage of packaging chiplets is that a chip designer can mix and match processor components. The most performance sensitive chiplets can be built with the latest generation manufacturing process, a premium option, but less critical parts can be built with older, cheaper processes, with chiplets that have already proven themselves.

Designers “can focus on more innovative engineering and less turning the crank on basic stuff,” Kanter said.

Chiplets also smooth over Intel’s manufacturing problems. Three of Meteor Lake’s four data-processing chiplets are built by its top rival, TSMC. Intel designed all the components but will only build the chiplet with the CPU cores.

And chiplets can let chip designers embrace new manufacturing faster. Instead of having to wait while engineers update every type of transistor for a more advanced photolithography process, chipmakers can adopt the new process just for the most performance sensitive chip tasks.

Advanced packaging adds cost, complexity and new manufacturing steps, so it’s not always the best choice. It also doesn’t fix woes like the problems that delayed Intel’s Sapphire Rapids and Ponte Vecchio. Increasingly, though, it’ll be key to chips in just about every PC for sale.